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mc145402 motorola 1 advance information the mc145402 is a 13bit linear monotonic digitaltoanalog and analog todigital converter implemented in a single silicongate cmos ic. potential applications include analog interface for digital signal processor (dsp) applications, high speed modems, telephone systems, sonar, adaptive differential pulse code modulation (adpcm) converters, echo cancellers, repeaters, voice synthesizers, and music synthesizers. ? 60 db signalto(noise plus distortion) ratio typical ? onchip precision voltage reference ? serial data ports ? two's complement coding ? 5 v supply operation ? sample rates from 100 hz to 16 khz (both a/d and d/a), 100 hz to 21.3 khz (a/d only), and 100 hz to 64 khz (d/a only) ? input sample and hold provided onchip ? 5 v cmos inputs; outputs capable of driving two lsttl loads ? available in a 16pin dip ? low power consumption: 50 mw typical, 1 mw powerdown block diagram bandgap voltage reference sample and hold d/a converter data selector receive latch receive shift register 15 rdd 13 14 rdc rce 2 3 a out a in 7 10 12 11 tdf tde tdc tdd 65 4 16 8 1 9 v dd v ss v ag v dg msi cci pdi sequence controller sample and hold comparator/ op amp successive approximation register transmit latch transmit shift register this document contains information on a new product. specifications and information herein are subject to change without notice. order this document by mc145402/d semiconductor technical data pin assignment

l suffix ceramic package case 620 ordering information MC145402L ceramic package 16 1 16 15 14 13 12 11 10 9 v ag a out a in pdi cci msi tdf v ss v dd rdd rce rdc tdc tde v dg tdd ? 1 2 3 4 5 6 7 8 ? motorola, inc. 1995
mc145402 motorola 2 absolute maximum ratings (voltages referenced to v ss ) rating symbol value unit dc supply voltage v dd v ss 0.5 to 11 v voltage, any pin to vss v 0.5 to v dd + 0.5 v dc current drain per pin (excluding v dd , v ss ) i 10 ma operating temperature range t a 40 to + 85 c storage temperature range t stg 85 to + 150 c recommended operating conditions parameter pins 0 to 70 c min 25 c typ 0 to 70 c max unit dc supply voltage v dd to v ss 9.5 10 10.5 v power dissipation, pdi = 1 v dd to v ss e 50 80 mw power dissipation, pdi = 0 v dd to v ss e 1 5 mw conversion rate full cycle a/d and d/a short cycle a/d short cycle d/a msi 0.1 0.1 0.1 e e e 16 21.3 64 khz conversion sequence rate cci 3.2 e 512 khz data rate tdc, rdc 16 x f msi e 4096 khz full scale analog levels (referenced to 600 w ) ai, ao e e 3.27 9.5 e e vp dbm digital electrical characteristics (v dd = 5 v, v ss = 5 v, v ag = v dg = 0 v, t a = 0 to 70 c) characteristic symbol min max unit high level input voltage v ih 3.5 e v low level input voltage v il e 1.5 v input current i in e 1.0 m a input capacitance c in e 10 pf high level output voltage tdd i out = 20 m a i out = 1 ma v oh 4.9 4.3 e e v low level output voltage tdd i out = 20 m a i out = 1 ma v ol e e 0.1 0.4 v this device contains circuitry to protect the inputs against damage due to high static voltages or electrical fields; however, it is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this high imped- ance circuit. for proper operation it is recom- mended that v in and v out be constrained to the range v ss (v in or v out ) v dd on analog inputs/outputs and v dg (v in or v out ) v dd on digital inputs/outputs. reliability of opera- tion is enhanced if unused digital inputs are tied to an appropriate logic voltage level (e.g., either v dg or v dd ) and unused analog inputs are tied to v ag .
mc145402 motorola 3 coder and decoder performance (v dd = 5 v 5%, v ss = 5 v 5%, v ag = v dg = 0 v, 0 dbm0 = 1.60 vrms = 6.30 dbm (600 w ), t a = 0 to 70 c, msi = tde = rce = 8 khz, tdc = rdc = 2.048 mhz, cci = 256 khz) ch i i coder (a/d) decoder (d/a) ui characteristic min typ max min typ max unit resolution 13 e 13 13 e 13 bits conversion time full cycle a/d and d/a short cycle a/d short cycle d/a 62.5 46.9 e e e e 10,000 10,000 e 62.5 e 15.6 e e e 10,000 e 10,000 m s differential nonlinearity e e 1 e e 1 lsb gain error 0.35 e + 0.35 0.35 e + 0.35 db offset 15 e e e + 15 e e 20 e e e + 20 lsb mv idle channel noise, 3 khz lowpass e 75 e e 79 e dbm0 signaltonoise 3.2 dbm0 (referenced to 1.02 khz through 0 dbm0 a f msi /2 lowpass filter) 10 dbm0 20 dbm0 30 dbm0 40 dbm0 50 dbm0 e e e e e e e 61 60 57 50 40 30 20 e e e e e e e e e e e e e e 62 60 59 52 42 32 22 e e e e e e e db analog electrical characteristics (v dd = 5 v 5%, v ss = 5 v 5%, v ag = v dg = 0 v, 0 dbm0 = 1.60 vrms = 6.30 dbm (600 w ), t a = 0 to 70 c, msi = tde = rce = 8 khz, tdc = rdc = 2.048 mhz, cci = 256 khz) characteristic pin symbol min typ max unit input current ai i in e 0.01 1 m a ac input impedance ai z in 0.5 e e m w input capacitance ai c in e e 15 pf output voltage range ao v out 3.4 e 3.4 v power supply rejection ratio (100 mv rms on v dd or v ss , 0 50 khz) ao, tdd psrr e 40 e db crosstalk, a in to a out and rdd to tdd referenced to 0 dbm0 @ 1.02 khz ao, tdd e e 90 75 db slew rate ao sr 1.5 3 e v/ m s settling time (full scale) ao t settle e 8 e m s
mc145402 motorola 4 switching characteristics (v dd = + 5 v 5%, v ss = 5 v 5%, v ag = v dg = 0 v, t a = 0 to 70 c, c l = 50 pf, see figure 1 ) characteristic symbol min max unit input rise time rce, rdc, tdc, tde, cci, msi t r e 100 ns input fall time rce, rdc, tdc, tde, cci, msi t f e 100 ns output rise time tdd t r e 80 ns output fall time tdd t f e 80 ns pulse width high rdc, msi, cci, tdc, rce t wh 100 e ns pulse width low tde, msi, tdc, rce, rdc t wl 100 e ns cci pulse width low t wl 500 e ns msi clock frequency f msi 0.1 64 khz cci clock frequency f cci 3.2 512 khz tdc and rdc clock frequency f dc 16 x f msi 4.1 mhz tdc rising edge to tdd data valid during tde high t p1 e 150 ns tde rising edge to tdd data valid during tdc high t p2 e 150 ns tde rising edge to tdd lowimpedance propagation delay t p3 0 100 ns tde falling edge to tdd highimpedance propagation delay t p4 e 40 ns tde rising edge to tdc falling edge setup time t su1 t su2 20 100 e e ns rdc bit 0 falling edge to last cci falling edge prior to msi t su3 20 e ns msi rising edge to cci falling edge setup time t su4 t su5 20 100 e e ns last cci rising edge (prior to msi) to tde rising edge t su6 100 e ns last cci rising edge (prior to msi) to first tdc rising edge t su6' 100 e ns first tdc falling edge to last cci rising edge prior to msi t su7 0 e ns rce rising edge to rdc falling edge setup time t su8 t su9 20 100 e e ns rdd valid to rdc falling edge setup time t su10 60 e ns rdd hold time from rdc falling edge t h 100 e ns
mc145402 motorola 5 t su1 tde tdc tdd msi cci rce rdd t su6 t su2 t p1 t p2 t p1 t p4 t su7 t p3 t wh t wl t su4 t su5 t su8 t su9 t su10 t h t su3 s b11 b10 b1 b0 t su6 cci last cci last figure 1. ac timing diagram last bit clock rdc
mc145402 motorola 6 pin descriptions v dd positive supply (pin 16) the most positive power supply, typically + 5 v in split power supply configurations, or + 10 v in single supply systems. v ss negative supply (pin 8) the most negative power supply, typically 5 v in split power supply configurations, or 0 v in single supply systems. v ag analog ground (pin 1) this is the analog signal reference point. this pin is nor- mally tied to 0 v in split supply operation or v dd /2 in single supply systems. v dg digital ground (pin 9) this is the ground reference for all of the digital input and output pins. cmos compatible logic signals swing from v dg to v dd where v dg can be established anywhere from v dd 4.75 v to v ss . a out analog output (pin 2) this is the output of the decoder's sample and hold circuit and is a 100% duty cycle analog output of the last digital word received and decoded by the decoder. a out is updated approximately 60 ns after the rising edge of the last cci prior to msi (see figure 2). a out is capable of driving a 10 k w , 50 pf load. a in analog input (pin 3) this is the highimpedance input to the coder. an a/d cycle begins on the first falling edge of cci following the ris- ing edge of msi. a in is sampled approximately 50 ns after the rising edge of cci prior to the start of the a/d cycle. pdi powerdown input (pin 4) in normal operation this input should be tied high. a logic low on this input puts the device into a minimum power dissi- pation mode. during powerdown, all functions stop. two complete msi conversion cycles are required to establish normal operation after leaving the powerdown mode. cci convert clock input (pin 5) this input controls the complete conversion sequence dur- ing one msi cycle and must receive a clock which is 32 times the frequency of msi. the only exception to 32 times the fre- quency of msi is during shortcycle operation. see general modes of operation section. cci must be synchronous and approximately rising edge aligned with msi. msi master sync input (pin 6) this pin determines the conversion rate for both the coder and the decoder. one a/d and d/a conversion takes place during each period of the digital clock applied to this input (except in shortcycle operation, see general modes of operation section). msi must be synchronous and approxi- mately rising edge aligned with cci. tdc transmit data clock (pin 12) digital data from the coder is serially transmitted from tdd on rising tdc edges whenever tde is a logic high. tdc must be approximately rising edge aligned with tde. gener- ally, if tdc is low when tde rises, the first rising edge of tdc clocks the first data bit. if tdc is high when tde rises, the first bit will be clocked by tde and the first rising edge of tdc after tde rises will clock out the second data bit. tde transmit data enable (pin 10) this pin is used to initiate the serial transfer of data from the coder and provides threestate control of the tdd pin. the rising edge of tde (or tdc if it follows tde) signals the start of data transfer from the tdd pin. a resulting high logic level on tde also releases tdd from its highimpedance state. tde must remain high throughout the data transfer to keep tdd in the lowimpedance state and must return to a low state prior to each data transfer. if tde remains high for more than 16 tdc clocks, the 16 bits of tdd data will be re- circulated. (note: the a/d cycle begins on the first falling edge of cci after the rising edge of msi. the internal trans- mit latch is updated one and one half cci periods prior to the start of the a/d cycle. a pulse generated by the logical and of tde and the first tdc transfers data to the transmit shift register, and this pulse must not occur when the transmit latch is updated. see figure 2 and see t su6 , t su6 , and t su7 of figure 1. tdd transmit digital data (pin 11) this is the threestate output data pin from the coder and is controlled by the tde and tdc pins. tdd is in the high impedance state whenever tde is a logic low. the first data bit is output from tdd on the rising edge of tde (or tdc if it follows tde) and each subsequent bit is output on rising edges of tdc. two output data formats are available as de- scribed in the tdf pin description below. tdf transmit data format (pin 7) the 13bit digital output of the coder is available in one of two 16bit two's complement formats as determined by the state of this pin. a logic 0 at this pin causes the data from tdd to be in a 16bit signextended format as follows: ssssm ... l where s, m, and l represent the sign, most sig- nificant bit, and the least significant bit, respectively. a logic 1 on this pin formats the data as follows: sm ... lsss (see fig- ure 3). rdd data is not affected by the state of this pin and if a adigital loopbacko is needed (tdd data looped back into rdd), this pin should be high.
mc145402 motorola 7 rdc receive data clock (pin 13) receive digital data is accepted by the decoder on the first 13 falling edges of rdc after an rce rising edge. rce receive clock enable (pin 14) this pin identifies the beginning of a data transfer into the rdd pin of the decoder. the first 13 falling edges of rdc af- ter an rce rising edge will clock data into the decoder data input, rdd. rce must return low prior to each data transfer. since receive data is latched into the receive latch on the last cci falling edge prior to msi, data transfers may not span this falling edge of cci without loss of data. rdd receive digital data (pin 15) this pin is the data input to the decoder and is controlled by the rdc and rce pins described above. two's comple- ment data are loaded in the following sequence: sm ... l where s, m, and l represent the sign, most significant bit, and the least significant bit, respectively. only the first 13 bits clocked by rdc after rce rises will be accepted for decod- ing. any additional bits will be ignored (see figure 3). general information general modes of operation the mc145402 has three modes of operation; a afullo cycle mode and two ``shorto cycle modes. the full cycle mode al- lows simultaneous analogtodigital (a/d) and digitalto analog (d/a) operation. the short cycle modes allow either a/d only or d/a only operation. two msi cycles are required for the mc145402 to detect which operating mode has been selected. see figure 2 for full versus short cycle clocking. full cycle operation when operating in the full cycle mode, the mc145402 per- forms a 13bit a/d conversion followed by a 13bit d/a con version. full cycle operation is selected by using a cci frequency that is 32 times the frequency of msi. msi is the sample rate frequency. short cycle analogtodigital operation if cci is 24 times the frequency of msi, short cycle ana- logtodigital operation is selected. this allows a 13bit a/d conversion only. in this mode, the d/a is not operational and any data applied to the rdd input is ignored. short cycle digitaltoanalog operation short cycle digitaltoanalog operation is selected by using a cci clock frequency that is eight times the msi sam- ple rate. during short cycle d/a operation, a/d operation is disabled and digital data read from tdd is not valid. clocking recommendations for optimum differential nonlinearity performance, all data transitions on tdd and rdd should be limited to the first four cci cycles following the rising edge of msi. this may be achieved by setting msi = tde = rce having a duration of 16 data clock cycles, and tdc = rdc 4 x cci clock frequency. figure 6 shows a circuit that generates this clock- ing configuration; see application circuits section. signal to distortion ratio figures 4 and 5 show graphs of typical signal to distortion ratios versus signal level for the mc145402. the presented data is referenced to a 1020 hz input sinusoidal frequency with signal levels referenced to 600 w and transmission level point adjusted (e.g., 0 dbm0 at 600 w with a tlp of 6.30 db is 4.53 v peaktopeak). for comparison, ideal signal to noise ratios for 9, 10, 11, 12, and 13bit a/d and d/a converters are also shown. the equation used for an ideal rms to rms signal to distortion ratio is: s/d = n x 6 db + 1.76 db where n is the number of bits of resolution, 6 db per bit, and 1.76 = 20 log ( 3 / 2 ). ( 3 / 2 ) is approximately the rms to rms ratio of a sine wave to white noise. the signal to noise plus distortion ratio is measured through a brickwall lowpass filter set to the nyquist frequen- cy of the a/d and d/a sample rate. for an 8 khz sample rate, the lowpass filter is set to block all signals above 4 khz. application circuits figure 6 shows a typical circuit for generating the clock frequencies for the mc145402. this circuit uses an mc74hc4040 and a 2.048 mhz crystal to generate the 256 khz frequency for internal sequencing, 1.024 mhz for the date clocks, and an 8 khz sample frequency. a 4.096 mhz crystal could be used for a sample rate of 16 khz. figure no tag shows the mc145402 interfaced to the dsp56000 digital signal processor. the dsp56000 can in- ternally generate the clocks for the mc145402 using the ssi serial interface. sck provides the sequencing and data clocks (nongated continuous dock) and sc2 (setup as the frame sync out, fsl = 0) provides the sample rate and data enables for the mc145402. the dividebyfour circuit to generate the cci clock is recommended for optimum mc145402 performance, and allows the dsp56000 to clock data in and out of the mc145402 quickly, leaving time avail- able for processing by the dsp before another sample is available. sc0 and sc1 could be used to gate the enables to select up to four devices on the ssi bus. telephone system transmission level point for a linear a/d or d/a converter referenced to mulaw companding mulaw companding, as specified by at&t and ccitt, requires 8159 quantization levels to implement both a/d and d/a conversion schemes. this is to be mirrored about signal ground for the negative part of the wave form. to implement a 13bit ( 12bit) linear converter scheme requires 8192 quantization levels mirrored about signal ground. to specify this converter such that it can be used to interface with, or as an alternative to, telephony based mu law applications, the following is an explanation of the gain translation. a 13bit linear converter scheme has 8192 quantization levels. the goal is to be able to convert between these two encoding schemes with minimal distortion. this dictates set- ting the lsbs to the same level. for this to be achieved re- quires the reference voltage of the linear converter to be
mc145402 motorola 8 8192/8159 times the reference voltage of the mulaw converter. the peak amplitude of a mulaw converter is 3.17 dbm0. the peak level of the linear converter will be 8192/8159 times the peak level of the mulaw converter, which is 8192/8159 x 3.17 dbm0. however, you cannot multi- ply a gain factor by a dbm value without using common term units and math (i.e., we must convert this gain factor to a db equivalent), which is: 20 log 10 (8192/8159) = 0.03 db with the gain factor in db, we can add it to the mulaw peak level: 3.17 dbm0 + 0.03 db = 3.20 dbm0 therefore, the linear converter peak level is 3.20 dbm0. this is another way of saying the 0 dbm0 level for the lin- ear converter is 3.20 db below the maximum amplitude. to determine the absolute 0 dbm0 level for the linear con- verter from the peak level, we calculate the peak level in dbm by: 10 log 10 3.27 vpk / 2 ) / (600 w ) 1 mw = 9.50 dbm (600 w ) and 3.20 db below this level is the 0 dbm0 absolute ampli- tude, which is 9.50 dbm 3.20 db = 6.30 dbm (600 w ) therefore, the calibration level, or transmission level point (tlp), for this part is 6.30 dbm (600 w ), which is 1.6 vrms based on the reference voltage of 3.27 v.
mc145402 motorola 9 ao updated and full cycle a/dd/a short cycle a/d only short cycle d/a only a/d conversion a/d conversion a/d conversion ai sampled ai sampled ao updated 1 8 16 24 32 msi msi msi cci cci cci tdd data transferred into d/a conversion d/a conversion d/a conversion d/a conversion d/a conversion rdd data latched into the receive latch rdd data latched into the receive latch the transmit latch tdd data transferred into the transmit latch clock cycle figure 2. mc145402 full and short cycle timing
mc145402 motorola 10 tde tdc rce rdc rdd tdd (tdf = 1) tdd (tdf = 0) s s s s s ssss b0 b9 b11 b10 b8 b7 b6 b5 b4 b3 b2 b1 b0 b9 b11 b10 b8 b7 b6 b5 b4 b3 b2 b1 b0 b9 b11 b10 b8 b7 b6 b5 b4 b3 b2 b1 figure 3. mc145402 digital data timing
mc145402 motorola 11 (1020 hz referenced to 600 input level (dbm0) w ) 80 70 60 50 40 30 20 10 0 60 50 40 30 20 10 0 10 13bit 12bit 11bit 10bit 9bit rms signal to rms (noise + distortion) (db) f msi /2 compared to 913 bit ideal a/d; msi = 8 khz; measured through a lowpass filter with a bandwidth of figure 4. mc145402 encoder (a/d) signal to noise plus distortion ratio (1020 hz referenced to 600 input level (dbm0) w ) 80 70 60 50 40 30 20 10 0 60 50 40 30 20 10 0 10 13bit 12bit 11bit 10bit 9bit rms signal to rms (noise + distortion) (db) f msi /2 compared to 913 bit ideal d/a; msi = 8 khz; measured through a lowpass filter with a bandwidth of figure 5. mc145402 decoder (d/a) signal to noise plus distortion ratio
mc145402 motorola 12 a/d 2.048 mhz 15 m 20 pf 20 pf mc74hcu04 + 5 v 0 v v dd v cc 16 10 8 clk gnd r 9 6 2 4 13 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 v ss v dg 15 13 14 7 11 12 10 5 6 4 + 5 v 8 khz 256 khz + 5 v mc145402 control 2 3 16 8 9 1 out rdd rdc rce tdf tdd tdc tde cci mis pdi + 5 v 5 v 0 v m f 0.1 m f 0.1 v cc gnd, pin 7 = 0 v , pin 14 = + 5 v 13bit power connections mc74hcu04 and mc74hc11 mc74hc11 1/3 mhz 1.024 data serial in data serial out voltage analog out voltage analog in d/a 13bit 11 mc74hc4040 v ag a in a w figure 6. typical mc145402 configuration
mc145402 motorola 13 + 5 v 128 f sample 32 f sample f sample + 5 v + 5 v + 5 v v cc v ss 256 khz 1.024 mhz 8 khz dsp56000 1/2 mc74hc74 1/2 mc74hc73 1/2 mc74hc73 1/2 mc74hc74 sck sc2 srd std pdi a in a out tdf v ag v dg cci tdc rdc tde rce msi tdd rdd clk clk clk clk d d r r r r j j k k q q q q q q q q v out v in v ss v dd mc145402 5 v figure 7. the mc145402, 13bit linear codec, interfaced to a motorola dsp56000, digital signal processor, ssi port
mc145402 motorola 14 package dimensions l suffix ceramic case 62009 min min max max inches millimeters dim 19.05 6.10 e 0.39 1.40 0.23 e 0 0.39 19.55 7.36 4.19 0.53 1.77 0.27 5.08 15 0.88 0.750 0.240 e 0.015 0.055 0.009 e 0 0.015 0.770 0.290 0.165 0.021 0.070 0.011 0.200 15 0.035 1.27 bsc 2.54 bsc 7.62 bsc 0.050 bsc 0.100 bsc 0.300 bsc a b c d e f g j k l m n notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension f may narrow to 0.76 (0.030) where the lead enters the ceramic body. d 16 pl j 16 pl seating plane 0.25 (0.010) t a m s 0.25 (0.010) t b m s 18 9 16 -a- -b- k c n g e f -t- m l
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mc145402 motorola 16 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters can and do vary in different applications. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa / europe : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, toshikatsu otsuki, p.o. box 20912; phoenix, arizona 85036. 18004412447 6f seibubutsuryucenter, 3142 tatsumi kotoku, tokyo 135, japan. 0335218315 mfax : rmfax0@email.sps.mot.com t ouchtone (602) 2446609 hong kong : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok r oad, tai po, n.t., hong kong. 85226629298 mc145402/d
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